Embodiments of the invention relate to an apparatus for manufacturing a semiconductor device and a method for manufacturing the semiconductor device using the same.
Recently, as a semiconductor device has rapidly become highly integrated and operated at a high speed, the dimension of a transistor has become gradually reduced. As the integration degree of a transistor increases, the dimension of interconnection of the semiconductor device becomes reduced. As a result, signals applied to the interconnection may be delayed or distorted and thus a high-speed operation of the semiconductor device can be interrupted.
In order to solve such a problem, a copper interconnection has been rapidly developed. The copper interconnection uses copper, which has resistance lower than that of aluminum or aluminum alloy that has been widely utilized as interconnection material of a semiconductor device and that has higher electro-migration.
In general, in order to form a copper interconnection, processes for forming and etching a copper layer are necessary. However, the copper layer has poor etching uniformity and the surface of the copper interconnection is rapidly oxidized while the copper layer is being etched.
In order to solve such a problem, a damascene process has been recently developed to form a copper interconnection.
According to the damascene process, a via hole and/or a trench are formed in an insulation layer, a copper layer is deposited in the trench and the via hole, and then the copper layer is planarized through a Chemical Mechanical Polishing (CMP) process, thereby forming a copper interconnection in the trench and the contact hole. That is, in the damascene process, since the copper interconnection is formed without etching the copper layer, the problem can be solved in which the copper interconnection is oxidized while the copper layer is being etched.
The afore-described damascene process can also be used for forming the bit or word lines of a semiconductor device in addition to a metal interconnection. In particular, according to the damascene process, contact holes (or via holes) for interconnecting an upper metal interconnection and a lower metal interconnection in a multilayer metal interconnection can be simultaneously formed, and a step coverage caused by the metal interconnections can be removed.
However, the copper interconnection having such advantages also has problems in that copper ions included therein are diffused so that the properties of the copper interconnection may deteriorate, and short-circuit may occur between adjacent copper interconnections.
In order to solve such a problem, a diffusion barrier is generally formed on the inner walls of a trench and/or a via hole in order to prevent the diffusion of copper atoms or ions into the insulation layer and/or oxygen atoms from the insulation layer into the copper. The diffusion barrier mainly has a TaN/Ta double layer structure (i.e. a TaN layer on a Ta layer), and is formed through a Physical Vapor Deposition (PVD) process such as a sputtering process. However, when forming a TaN/Ta double layer through the PVD process, step coverage may be less than ideal or satisfactory, and contact resistance of the via/contact may be reduced. As a result, research into a method for forming a TaN layer or a Ta layer through an Atomic Layer Deposition (ALD) process has been recently pursued. However, when forming the TaN layer or the Ta layer through the ALD process, the procedure becomes complicated and the productivity is significantly reduced.
Further, the TaN layer or the Ta layer used as a diffusion barrier increases resistivity and/or electro-migration properties of the conductive layer(s) in a semiconductor device.